1. Field of the Invention
The invention relates to the field of interlayer connections in semiconductor devices using a copper damascene structure.
2. Prior Art
In current integrated circuits, several layers of interconnect structures fabricated above a substrate containing active devices are often used. Each interconnect layer is fabricated in, or on, an interlayer dielectric (ILD). Vias are formed in each ILD to make contact with conductors in underlying layers. It is generally accepted that the dielectric material in each ILD should have a low dielectric constant (k) to obtain low capacitance between the conductors.
Copper damascene structures are often used in conjunction with the ILDs to provide the interconnect structure. Typically, the copper is planarized using chemical-mechanical polishing (CMP) because of the difficulties of chemically etching copper.
A problem arises where low k dielectrics are used in conjunction with a copper damascene structure. The low k dielectrics are inherently mechanically weak, and consequently, not particularly suitable for the stresses associated with the CMP.
Articles discussing low k dielectrics are: xe2x80x9cFrom tribological coatings to low-k dielectrics for ULSI interconnects,xe2x80x9d by A. Grill, Thin Solid Films 398-399 (2001) pages 527-532; xe2x80x9cIntegration Feasibility of Porous SiLK Semiconductor Dielectric,xe2x80x9d by J. J. Waeterloos, et al., IEEE Conference Proceedings, IITC, (June 2001) pages 253-254; and xe2x80x9cLow-k Dielectrics Characterization for Damascene Integration,xe2x80x9d by Simon Lin, et al., IEEE Conference Proceedings, IITC, (June 2001) pages 146-148.